| 摘要 |
PROBLEM TO BE SOLVED: To prevent a silicide layer 12b of a wiring layer 12 comprising the silicide layer 12b as an uppermost layer formed on an element isolation insulating film 8a and a polysilicon layer 12a as a lower layer from being overetched to disappear when a contact hole 20a etc., are formed by dry etching in an inter-layer insulating film IL having its surface ground in a CMP step to be flattened. SOLUTION: A level difference is generated even on a surface of an N-type epitaxial layer 4 owing to a silicon level difference formed during formation of an N+ type buried layer 2. The element isolation insulating film 8a is formed on a P-type separation layer 5 formed at a high part of the level difference. The wiring layer 12 comprising the silicide layer 12b as the upper layer and the polysilicon layer 12a as the lower layer is formed on the element isolation insulating film 8a, but before the wiring layer 12 is formed, the element isolation insulating film 8a is made thin to make the level difference between a surface of the silicide layer 12b as the uppermost layer and a surface of the N+ type source layer 15 and the like smaller than it has been before the element isolation insulating film 8a is made thin. COPYRIGHT: (C)2011,JPO&INPIT
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