| 摘要 |
The invention relates to a computer processor comprising a decode unit for decoding a stream of instruction packets from a memory, each instruction packet comprising a plurality of instructions; a processing channel comprising a plurality of functional units and operable to perform control processing operations; wherein the decode unit is operable to receive and decode instruction packets of a bit length of 64 bits and to detect if the instruction packet defines three control instructions each having a bit length of 21 bits and wherein when the decode unit detects that the instruction packet comprises three such control instructions said control instructions are supplied to the processing channel for execution in the order in which they appear in the instruction packet, said detection using an identification bit in the instruction packet.
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