发明名称 Tri-layered power scheme for architectures which contain a micro-controller
摘要 Various embodiments are directed to a tri-layered power scheme for architectures which contain a microcontroller. In one embodiment, a power management system may comprise a microcontroller in a chipset, a low consumption power well to control a power supply to the microcontroller, and a power controller to control a power supply to the low consumption power well. The power management system may be arranged to switch among multiple power consumption states. In a maximum power consumption state, the microcontroller is on, the power controller is on, and the low consumption power well is on. In an intermediate power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is required to be on. In a minimum power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is optionally on or off at the discretion of the power controller. Other embodiments are described and claimed.
申请公布号 US7900072(B2) 申请公布日期 2011.03.01
申请号 US20070963215 申请日期 2007.12.21
申请人 INTEL CORPORATION 发明人 BERGER MICHAEL;DERR MICHAEL;RESCH JOSHUA;KATARIA MUKESH;GEDEON MAZEN;KUPERMANN ELI;VICK JEFFREY JOHN
分类号 G06F1/00;G06F1/26;G11C5/14;H04M1/00 主分类号 G06F1/00
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