发明名称 Method to produce an electrical model of an integrated circuit substrate and related system and article of manufacture
摘要 A method is provided to produce a model of an integrated circuit substrate, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; and connecting the mapped tile instances to each other to produce a tile grid that models overall electrical behavior of the substrate.
申请公布号 US7900166(B2) 申请公布日期 2011.03.01
申请号 US20070769675 申请日期 2007.06.27
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 KARIAT VINOD;DONG XIAOPENG;NOICE DAVID
分类号 G06F17/50;G06F9/45 主分类号 G06F17/50
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