发明名称 |
Integrated circuit characterisation system and method |
摘要 |
There is presented a system and method for characterizing an integrated circuit (IC) for comparison with a pre-defined system-level characteristic related to an aspect of IC operation, wherein a test procedure on the IC that invokes this aspect is executed, while at least one operational bottleneck is invoked to constrain operation of the IC to exhibit a system-level operation thereof related to the aspect. Data generated via the test procedure in response to the bottleneck is collected and the system-level operation exhibited thereby is compared for consistency with the pre-defined system-level characteristic.
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申请公布号 |
US7899640(B2) |
申请公布日期 |
2011.03.01 |
申请号 |
US20080183298 |
申请日期 |
2008.07.31 |
申请人 |
SEMICONDUCTOR INSIGHTS INC. |
发明人 |
ZAVADSKY VYACHESLAV L.;SHERSTYUK MYKOLA |
分类号 |
G06F11/26;G06F11/00 |
主分类号 |
G06F11/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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