发明名称 |
Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations |
摘要 |
Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the execution unit. The execution unit has logic that implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA). The floating point vector registers of the vector register file store both scalar and floating point values as vectors having a plurality of vector elements. The processor may be part of a data processing system.
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申请公布号 |
US7900025(B2) |
申请公布日期 |
2011.03.01 |
申请号 |
US20080250575 |
申请日期 |
2008.10.14 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GSCHWIND MICHAEL K. |
分类号 |
G06F9/305 |
主分类号 |
G06F9/305 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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