发明名称 |
Methods of fabricating vertical twin-channel transistors |
摘要 |
A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.
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申请公布号 |
US7897463(B2) |
申请公布日期 |
2011.03.01 |
申请号 |
US20100651688 |
申请日期 |
2010.01.04 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
YUN EUN-JUNG;LEE SUNG-YOUNG;KIM MIN-SANG;KIM SUNG-MIN;CHO HYE-JIN |
分类号 |
H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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地址 |
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