SEMICONDUCTOR MEMORY DEVICE HAVING MEANS FOR CONTROLLING BITLINE LOADING

摘要

PURPOSE: A semiconductor memory device is provided to improve the sensing speed and performance of a bit line sensing amplifier by reducing influences due to the threshold voltage mismatch between the transistors inside a bit line sensing amplifier. CONSTITUTION: A bit line(BL_L,BL_R) is connected to a plurality of memory cells within a memory cell array block(M_L,M_R). One end of an isolation transistor(IST_L,IST_R) is connected to the bit line. A sense amplifier(11) has a first node and a second node. The first node is connected to the other end of the isolation transistor. The second node is not connected to the bit line on the memory cell array block. A word line supply voltage, a ground voltage, and a middle voltage are selectively applied to the gate of the isolation transistor.