| 摘要 |
Digital background calibration in a pipelined ADC is performed by extracting a capacitor mismatch value &Dgr; that represents a mismatch between a sampling capacitor C1 and a feedback capacitor C2 in the pipelined ADC, and using &Dgr; to correct the capacitor mismatch error. &Dgr; is extracted by performing commutated feedback capacitor switching (CFCS) in a background correlation loop. The error caused by the capacitor mismatch is calibrated out by subtracting the error from a digital output Dout of the pipelined ADC. Convergence speed may be accelerated and convergence accuracy may be increased during digital background calibration of pipelined ADCs, by using a higher order LPF. A bandwidth switching scheme may be implemented by the LPF, i.e. a larger bandwidth may be utilized during calibration start-up to increase convergence speed during start-up and a smaller bandwidth may be utilized during steady state to increase convergence accuracy during steady state.
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