发明名称 DATA RECEPTION CIRCUIT
摘要 <p>Difference of a constant delay between a rising edge and a falling edge of a data signal can be reduced. A data reception circuit comprises an amplification circuit which amplifies and outputs a data signal which transmits data, a first delay circuit which delays the output from the amplification circuit in accordance with a first control signal and outputs as a first delay data signal, a second delay circuit which delays the output from the amplification circuit in accordance with a second control signal and outputs as a second delay data signal, and a data signal reproduction circuit which generates and outputs a reproduction data signal on the basis of an active edge of the first delay data signal and an active edge of the second delay data signal.</p>
申请公布号 WO2011021357(A1) 申请公布日期 2011.02.24
申请号 WO2010JP04944 申请日期 2010.08.05
申请人 PANASONIC CORPORATION;TAKEDA, NORIAKI 发明人 TAKEDA, NORIAKI
分类号 H03K5/1532;G06F12/00;G06F13/42;H03K5/13 主分类号 H03K5/1532
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