Configuration of shared tester channels to avoid electrical connections across die area boundary on a wafer

摘要

A process or apparatus for testing a plurality of semiconductor dies on a semiconductor wafer utilizing a tester configured to test the dies in groups can include controlling as a logical whole provision of first test signals through a plurality of first communications channels to first probes organized into a plurality of N first probe die groups each configured to contact a different one of the dies of the wafer. One of the first communications channels can be a first common communications channel connected to probes in X of the N first probe die groups but not to probes in Y of the N first probe die groups. X can be at least two and Y can be at least one. The process can also include controlling as a logical whole provision of second test signals through a plurality of second communications channels to second probes organized into a plurality of second probe die groups each configured to contact a different one of the dies of the wafer. One of the second communications channels can be a second common communications channel connected to probes in all of the second probe die groups and probes in each of the Y of the first probe die groups.