发明名称 |
HVNMOS structure for reducing on-resistance and preventing BJT triggering |
摘要 |
A high-voltage metal-oxide-semiconductor (HVMOS) device and methods for forming the same are provided. The HVMOS device includes a substrate; a first high-voltage n-well (HVNW) region buried in the substrate; a p-type buried layer (PBL) horizontally adjoining the first HVNW region; a second HVNW region on the first HVNW region; a high-voltage p-well (HVPW) region over the PBL; an insulating region at a top surface of the second HVNW region; a gate dielectric extending from over the HVPW region to over the second HVNW region, wherein the gate dielectric has a portion over the insulating region; and a gate electrode on the gate dielectric.
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申请公布号 |
US7893490(B2) |
申请公布日期 |
2011.02.22 |
申请号 |
US20070796832 |
申请日期 |
2007.04.30 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
HUANG YU-HUI;LI TING-PANG;CHEN FU-HSIN |
分类号 |
H01L29/66 |
主分类号 |
H01L29/66 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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