发明名称 Semiconductor storage device comprising reference cell discharge operation load reduction
摘要 A semiconductor storage device precharging a bit line pair to a ground potential includes a sense amplifier connected between the bit line pair, a storage cell connected to one of the bit line pair and storing data, a first transistor controlling a conduction state between the other of the bit line pair and a reference cell node, a second transistor connected between a reference voltage source generating a reference voltage and the reference cell node, the second transistor exclusively controlled from the first transistor, and a capacitor setting a potential of the reference cell node.
申请公布号 US7894279(B2) 申请公布日期 2011.02.22
申请号 US20080252548 申请日期 2008.10.16
申请人 RENESAS ELECTRONICS CORPORATION 发明人 MASUDA TAKAFUMI;SERIZAWA KENICHI;TAKAHASHI HIROYUKI
分类号 G11C5/14 主分类号 G11C5/14
代理机构 代理人
主权项
地址