发明名称 Circuit for protecting NMOS device from voltage stress
摘要 A protection circuit for an NMOS device is provided. The protection circuit includes a cascoding NMOS transistor and an adjusting circuit. The cascoding NMOS transistor is cascoded between the NMOS device and an external voltage source. The adjusting circuit is coupled to the external voltage source, a gate of the cascoding NMOS transistor, and an internal voltage source. The adjusting circuit adjusts the voltage at the gate of the cascoding NMOS transistor according to the voltages of the external voltage source and the internal voltage source so as to protect the NMOS device from a voltage stress caused by the external voltage source.
申请公布号 US7894171(B2) 申请公布日期 2011.02.22
申请号 US20080155613 申请日期 2008.06.06
申请人 MSTAR SEMICONDUCTOR, INC. 发明人 YEH CHUN-WEN
分类号 H02H9/00 主分类号 H02H9/00
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