| 摘要 |
PROBLEM TO BE SOLVED: To hold data consistency of a cache memory and a real memory and to reduce CPU processing loads. SOLUTION: A DMA (direct memory access) controller for controlling data transfer in a microprocessor system including a cache function includes a transfer control means for performing transfer control based on the alignment information of a cache line size, so that loads for calculating a consistency cancel area by CPU calculation processing in order to hold the consistency of the cache memory and the memory device during DMA transfer can be eliminated. COPYRIGHT: (C)2011,JPO&INPIT |
