| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an interface circuit for allowing a circuit which outputs a clock signal to correctly receive reception data regardless of wiring delay/IO cell delay in transmitting/receiving data in synchronization with a single clock signal, and to provide a semiconductor device provided with the same. <P>SOLUTION: The interface circuit 2 includes a reception data adjustment circuit 5. The reception data adjustment circuit 5 selects a reception data port whose start bit is fetched with optimal timing among a first reception data port to an n-th reception data port, outputs its pointer as a selection signal SEL to a first selection circuit 7 for selecting a reception data port and a second selection circuit for selecting a plurality of clock signals whose phases are shifted, and inputs the selected data and a clock signal to a non-synchronous absorption FIFO 11. <P>COPYRIGHT: (C)2011,JPO&INPIT |
