发明名称 APPARATUS AND METHOD FOR MEMORY MANAGEMENT AND EFFICIENT DATA PROCESSING
摘要 Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.
申请公布号 WO2011020055(A1) 申请公布日期 2011.02.17
申请号 WO2010US45520 申请日期 2010.08.13
申请人 QUALCOMM INCORPORATED;KOHLENZ, MATHIAS;MIR, IDREAS;KHAN, IRFAN ANWAR;SATHYANARAYAN, MADHUSUDAN;MAHESHWARI, SHAILESH;KRISHNAMOORTHY, SRIVIDHYA;URGAONKAR, SANDEEP;KLINGENBRUNN, THOMAS;LIOU, TIM TYNGHUEI 发明人 KOHLENZ, MATHIAS;MIR, IDREAS;KHAN, IRFAN ANWAR;SATHYANARAYAN, MADHUSUDAN;MAHESHWARI, SHAILESH;KRISHNAMOORTHY, SRIVIDHYA;URGAONKAR, SANDEEP;KLINGENBRUNN, THOMAS;LIOU, TIM TYNGHUEI
分类号 G06F9/50 主分类号 G06F9/50
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