| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an arithmetic processing unit that increases the efficiency of register usage. <P>SOLUTION: When a set data processing instruction to process set data having first and second data is decoded, allocable registers 15a and 16a are selected. The result of processing of the first data by a processing part 13 is stored in the allocable register 15a, and the result of processing of the second data by a processing part 14 is stored in the allocable register 16a. The processing results stored in the allocable registers 15a and 16a are then stored in result registers 17a and 18a respectively. When a normal data processing instruction to process third data is decoded, meanwhile, either of the allocable registers 15a and 16a is selected. If the third data is processed by the processing part 13, the processing result is stored in the allocable register 15a and then stored in the result register 17a. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
