Parity-Preserving Reversible Logic Gate, TG gate and full adder using it,申请号KR20090044090-传众专利搜索

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发明名称	Parity-Preserving Reversible Logic Gate, TG gate and full adder using it
摘要
申请公布号	KR101015122(B1)	申请公布日期	2011.02.16
申请号	KR20090044090	申请日期	2009.05.20
申请人		发明人
分类号	G06F7/00;G06F7/50;H03K19/00	主分类号	G06F7/00
代理机构		代理人
主权项
地址

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