Process for forming integrated circuits with both split gate and common gate FinFET transistors

摘要

A method is disclosed for forming an integrated circuit including a common gate FinFET device and a split gate FinFET device. Taller fins and shorter fins of different heights are formed in a semiconductor surface. Layers of gate dielectric material and gate electrode material are formed over tops and sides of the fins. The gate electrode material layer is planarized using chemical-mechanical polishing to remove the gate electrode material from the tops of the taller fins, leaving the gate electrode material over the tops of the shorter fins. The planarized material is patterned to form split (dual) gate structures on the sides of the taller fins and common gate structures on the tops and sides of the shorter fins.