发明名称 Delegated write for race avoidance in a processor
摘要 In a system including multiple-slice processors and memories, a synchronization unit with race avoidance capability includes a delegated write engine that receives data and memory address information from the processors and writes data to the memory as a delegate for the processors.
申请公布号 US7890706(B2) 申请公布日期 2011.02.15
申请号 US20040990151 申请日期 2004.11.16
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 GARCIA DAVID J.;KNOWLES MICHAEL;HEYNEMANN TOM A.;SPROUSE JEFFREY A.
分类号 G06F13/14;G06F9/46;G06F11/00;G06F11/16;G06F11/18;G06F12/00 主分类号 G06F13/14
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