发明名称 Processing unit incorporating L1 cache bypass
摘要 A circuit arrangement and method bypass the storage of requested data in a higher level cache of a multi-level memory architecture during the return of the requested data to a requester, while caching the requested data in a lower level cache. For certain types of data, e.g., data that is only used once and/or that is rarely modified or written back to memory, bypassing storage in a higher level cache reduces the likelihood of the requested data casting out frequently used data from the higher level cache. By caching the data in a lower level cache, however, the lower level cache can still snoop data requests and return requested data in the event the data is already cached in the lower level cache.
申请公布号 US7890699(B2) 申请公布日期 2011.02.15
申请号 US20080972221 申请日期 2008.01.10
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 COMPARAN MIGUEL;MEJDRICH ERIC OLIVER;MUFF ADAM JAMES
分类号 G06F12/00 主分类号 G06F12/00
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