| 摘要 |
A data generator provides faster data than before. A parallel data generator 18 provides first data having four or five effective data width according to a divided clock DCLK. A bit width adjuster 20 having a FIFO memory receives the first parallel data to provide second parallel data of constant four bit width despite of the bit width of the first parallel data. A parallel to serial converter 12 converts the second parallel data into serial data according to a reference clock RCLK that is faster than divided clock DCLK. The frequency of the divided clock DCLK can be constant, which makes it possible to use DLL to fasten the operation of the logic circuits.
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