DELAY LOCKED LOOP AND DELAY LOCKING METHOD THEREOF

摘要

PURPOSE: A delay locked loop and a delay locking method thereof are provided to improve the reliability of a semiconductor device by generating a comp clock signal which is locked with an external clock signal. CONSTITUTION: A phase detector(230) respectively detects a rising edge phase difference and a falling edge phase difference. A duty cycle controller(250) selectively fixes the rising edge or falling edge of the first and second clock signals. The duty cycle controller generates a phase interpolator control signal and includes a rising edge lock detector and a falling edge lock detector. A phase interpolator(260) controls the pulse width of a second clock signal.