发明名称 |
Semiconductor memory circuit |
摘要 |
The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
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申请公布号 |
US2011032777(A1) |
申请公布日期 |
2011.02.10 |
申请号 |
US20100923338 |
申请日期 |
2010.09.15 |
申请人 |
RENESAS ELECTRONICS CORPORATION;HITACHI DEVICE ENGINEERING CO., LTD. |
发明人 |
AKIBA TAKESADA;UEDA SHIGELD;TACHIBANA TOSHIKAZU;HORIGUCHI MASASHI |
分类号 |
G11C5/14;G11C11/407;G11C11/401;G11C11/403;G11C11/406;G11C11/4074;G11C11/409;G11C29/08 |
主分类号 |
G11C5/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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