发明名称 |
Delay locked loop circuit and signal delay method |
摘要 |
A multiplier PLL multiplies a reference clock and outputs the multiplied clock. A DLL compares the clock output from the multiplier PLL with a clock obtained by delaying the clock output from the multiplier PLL. The DLL generates a delay signal having a given amount of delay based on the comparison result. A delay control signal operation circuit generates a delay control signal based on the delay signal generated by the DLL. A first delay circuit delays an input signal based on the delay control signal generated by the delay control signal operation circuit.
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申请公布号 |
US2011032014(A1) |
申请公布日期 |
2011.02.10 |
申请号 |
US20100801894 |
申请日期 |
2010.06.30 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
SHIHARA MASAHIKO;TANGODA ATSUSHI |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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