| 摘要 |
PURPOSE:To obtain a semiconductor memory device in which a write operation is performed with a timing at the front edge or the rear edge of a control signal selectively, by detecting a change timing signal to the low level or the high level of a write control signal respectively, and making either effective according to a switching control signal. CONSTITUTION:In an internal synchronous dynamic RAM, an address signal change detection circuit ATD, when the level of either out of address signals a0-A16 being changed, forms an address signal changes detecting pulse (phi) synchronized with the changed timing. An internal control signal generation circuit TG forms and sends a various kinds of timing signals required for a memory operation, based on two external control signals CE (chip enable signal) and WE (write enable signal), and the address signal change detection signal (phi). Since the dynamic RAM is operated by the timing signal formed in the inside, it is possible to operate it from the outside of an IC similarly as a static RAM.
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