发明名称 |
BUFFERING CIRCUIT WITH REDUCED DYNAMIC POWER CONSUMPTION |
摘要 |
A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit. The first and second amplifier circuits can have reduced output voltage ranges and hence reduced total power consumption.
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申请公布号 |
US2011032240(A1) |
申请公布日期 |
2011.02.10 |
申请号 |
US20090536050 |
申请日期 |
2009.08.05 |
申请人 |
HIMAX TECHNOLOGIES LIMITED |
发明人 |
WANG JIA-HUI;TSAI CHIEN-HUNG;CHEN YING-LIEH;CHANG CHIN-TIEN |
分类号 |
G09G5/00;H03F3/16;H03L5/00 |
主分类号 |
G09G5/00 |
代理机构 |
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地址 |
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