发明名称 VIDEO ENCODING AND DECODING DEVICE
摘要 Provided is a video encoding and decoding device which can use limited memory resources to maximize system performance. After a direct memory access means (160) of a motion-compensation device (101) generates a DMA request after an interpolation complete was received from an interpolation means (180), and a DMA ACK was received from a memory access arbitration means (110), a video encoding and decoding device (100) receives a plurality of DMA input data in accordance with the maximum DMA burst constraint and the block buffer size constraint, and generates the block memory address for storing the reference pixel data in a variable size block buffer (170) in accordance with the decoding parameters, the calculation process level Lc, the maximum DMA burst constraint, and the block buffer size constraint.
申请公布号 US2011032995(A1) 申请公布日期 2011.02.10
申请号 US20090937159 申请日期 2009.04.22
申请人 PANASONIC CORPORATION 发明人 CHUA TIEN PING;BI MI MICHAEL
分类号 H04N7/12 主分类号 H04N7/12
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