发明名称 |
Layout design method of semiconductor integrated circuit having well supplied with potential different from substrate potential |
摘要 |
Design time (TAT) is reduced in a layout design of a semiconductor integrated circuit having a well supplied with a potential different from a substrate potential. A layout design method of the present invention includes preparing a first cell pattern placed on a semiconductor substrate of a first conductive type, preparing a second cell pattern having a deep well of a second conductive type, placing the first cell pattern in a first circuit region, and placing the second cell pattern in a second region different from the first circuit region. This reduces TAT in chip design.
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申请公布号 |
US7884426(B2) |
申请公布日期 |
2011.02.08 |
申请号 |
US20060591550 |
申请日期 |
2006.11.02 |
申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
YODA KENICHI |
分类号 |
H01L27/092;H01L21/70;H01L27/088;H01L27/118;H01L29/02 |
主分类号 |
H01L27/092 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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