发明名称 |
Three dimensional twisted bitline architecture for multi-port memory |
摘要 |
Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.
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申请公布号 |
US7885138(B2) |
申请公布日期 |
2011.02.08 |
申请号 |
US20070875173 |
申请日期 |
2007.10.19 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KIM HOKI;KIRIHATA TOSHIAKI |
分类号 |
G11C8/00 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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