CLOCK DATA RECOVERY CIRCUIT AND DISPLAY DEVICE

摘要

PURPOSE: A clock data recovery circuit and a display device are provided to reduce required time in order to detect the generation of a false lock by removing the necessity of calculating the generation probability of a pattern or a pattern which is at least 3 bits during a predetermined period. CONSTITUTION: A receiver circuit(20) receives serial data which includes a predetermined pattern. The receiver circuit generates sampled data by synchronizing the serial data with a clock signal. A phase locked loop circuit(30) generates the clock signal by restoring clock data based on the sampled data. A false lock detection circuit(40) detects the false lock of the PLL circuit by detecting the false lock pattern in the sampled data.