| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a circuit manufactured on a substrate, and a technique for reducing the problem of excessive overlap of a gate/channel lead. <P>SOLUTION: An array includes cells, each cell 16 has a bottom gate amorphous silicon thin film transistor (a-Si TFT) 20. Each a-Si TFT 20 has an undoped amorphous silicon layer 64 over its gate region 60 and extending beyond its edges 84, 86. Each a-Si TFT 20 also has an insulating region 66, having edges 80, 82 approximately aligned with the edges 84, 86 of its gate region 60. Two channel leads 70, 72 of doped semiconductor material, such as, microcrystalline silicon or polycrystalline silicon are on the undoped amorphous silicon layer 64, with each overlapping of an edge of the insulating region by a distance that is not more than a maximum overlap distance (1.0μm). <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
