发明名称 VERIFICATION SYSTEM AND METHOD FOR OPERATION CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To facilitate verification of an operation circuit and to reduce a required time. <P>SOLUTION: A description, such as "wire" showing wiring, is extracted as a description representing an internal signal from a circuit description showing an operation circuit 31 to be verified (step S11), on the basis of this, wiring of the internal signal of the operation circuit 31 is connected to an input terminal of a selection circuit 32, and a circuit description representing the operation circuit 31 to which the selection circuit 32 is connected is generated (step S12). On the basis of the circuit description generated, the operation circuit 31 to which the selection circuit 32 is connected is constructed in a semiconductor integrated circuit 7a (step S14). Also, mapping data representing a correspondence between the input terminal of the selection circuit 32 and the wiring of the internal signal connected to the same are generated and displayed (step S13). A designer refers to the mapping data and designates an address corresponding to a desired internal signal with respect to the selection circuit 32, so that a designated internal signal is selected and output from an output terminal of the semiconductor integrated circuit 7a. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011022893(A) 申请公布日期 2011.02.03
申请号 JP20090168746 申请日期 2009.07.17
申请人 FUJI ELECTRIC SYSTEMS CO LTD 发明人 SHINOHARA HIROSHI
分类号 G06F17/50;G01R31/28;G06F11/22 主分类号 G06F17/50
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