发明名称 PROGRAMMABLE DELAY GENERATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce a mounting area of a transmission line, to prevent mismatching of impedance, and to prevent accumulation of delay errors. SOLUTION: This programmable delay generation circuit includes: a first resistor having one end connected to an input time signal; a first transmission line having one end connected to the other end of the first resistor with the other end opened, and having the same value of impedance as the value of the first resistor; a first comparator having one input end connected to a connection point between the first resistor and the first transmission line, and the other input end connected to a first reference voltage; a second resistor having one end connected to the output of the first comparator; a second transmission line having one end connected to the other end of the second resistor with the other end opened, and having the same value of impedance as the value of the second resistor; and a second comparator having one input connected to a connection point between the second resistor and the second transmission line, and the other input connected to a second reference voltage. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011023925(A) 申请公布日期 2011.02.03
申请号 JP20090166505 申请日期 2009.07.15
申请人 YOKOGAWA ELECTRIC CORP 发明人 YAMADA TETSUHISA
分类号 H03K5/13 主分类号 H03K5/13
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