| 摘要 |
Clock circuits, memories and methods for generating a clock signal are described. One such clock circuit includes a delay locked loop (DLL) configured to receive a reference clock signal and generate an output clock signal having an adjustable phase relationship relative to the reference clock signal, and further includes a clock jitter feedback circuit coupled to a clock tree and the DLL. The clock jitter feedback circuit is configured to synchronize a clock jitter feedback signal and a DLL feedback signal that is based on the output clock signal. The clock jitter feedback circuit is further configured to provide the clock jitter feedback signal to the DLL for synchronization with a buffered reference clock signal. The clock jitter feedback signal is based on and generated in response to receiving a distributed output clock signal from the clock tree circuit and the buffered reference signal is based on the reference clock signal.
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