| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor device facilitating evaluation and management of production margin. <P>SOLUTION: The semiconductor device including a cell array has provided with a process failure detection circuits, having a layout pattern of the substantially same shape as that of the cell of the cell array in a dummy region provided in the periphery of the cell array. In particular, since the process failure detection circuits have the function as the dummy pattern provided in the peripheral part of the cell array, the chip surface for the process failure detection circuit is saved. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
