发明名称 PACKET TRANSMISSION CONTROL APPARATUS, HARDWARE CIRCUIT, AND PROGRAM
摘要 <p><P>PROBLEM TO BE SOLVED: To achieve complicated QoS control and transmit a packet at correct time. <P>SOLUTION: A packet type identification unit 101 identifies the type of a packet and enqueues the packet to a queue corresponding to the identified packet type among queues 102-1 to 102-n with QoS values set according to the corresponding packet type. For each packet in each queue, a scheduler unit 103 calculates estimated transmission time based on the QoS value of the queue, and dequeues the packet and outputs the packet to a hardware control unit 200 together with time information that indicates the estimated transmission time. A buffer storage processing unit 210 sorts the packets output from the scheduler unit 103 in the order of estimated transmission time, and stores the sorted packets in a buffer unit 220. A transmission processing unit 230 transmits each packet stored in the buffer unit 220 at the estimated transmission time of each packet. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2011024027(A) 申请公布日期 2011.02.03
申请号 JP20090168060 申请日期 2009.07.16
申请人 FUJITSU LTD 发明人 NAMIHIRA DAISUKE
分类号 H04L12/815;H04L12/863;H04L12/875 主分类号 H04L12/815
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