| 摘要 |
<p>A loadless static random access memory cell (200) includes four transistors (202, 204, 206, 208). The first transistor (202) has a gate terminal (220) corresponding to a word line, a source/drain terminal (222) corresponding to a first bit line (212), and a drain/source terminal (224) corresponding to a first storage node (226). The second transistor (204) has a gate terminal (230) corresponding to the word line (210), a source/drain terminal (232) corresponding to a second bit line (214), and a drain/source terminal (234) corresponding to a second storage node (236). The third transistor (206) has a gate terminal (240) coupled to the second storage node (236), a drain terminal (242) coupled to the first storage node (226), a source terminal (244) corresponding to a reference voltage, and a body terminal (246) directly connected to the third gate terminal (240). The fourth transistor (208) has a gate terminal (250) coupled to the first storage node (226), a drain terminal (252) coupled to the second storage node (236), a source terminal (254) corresponding to the reference voltage, and a body terminal (256) directly connected to the fourth gate terminal (250).</p> |
