| 摘要 |
A semiconductor wafer has a pre-alignment pattern including two or more notches on the wafer edge and the notches are used for wafer pre-alignment in fabrication processes. In one embodiment, at least two distances along the wafer edge between any adjacent notches are different. In another embodiment, distances along the wafer edge between any adjacent notches are each different. In another aspect, the pre-alignment pattern includes one or more notches on the wafer edge and one flat side on the wafer edge, wherein the notches and the flat side are used for wafer pre-alignment in fabrication processes. In one embodiment, at least two distances along the wafer edge between any adjacent notches or between the flat side and an adjacent notch are different. In another embodiment, distances along the wafer edge between any adjacent notches and between the flat side and an adjacent notch are each different. |
