发明名称 Circuit Arrangement and Method for Testing a Reset Circuit
摘要 A circuit arrangement (10) for testing a reset circuit (11) comprises the reset circuit (11) and a changeover switch (14). The reset circuit comprises a voltage input (12) for feeding an input voltage (VDD) and an output (13) for providing a reset signal (POR) as a function of the input voltage (VDD). The changeover switch (14) comprises a first input (15) for feeding a test voltage (VTM), a second input (16) for feeding a supply voltage (VBAT), a control input (17) for changing over between the first and the second input (15, 16) as a function of the test signal (TM), and an output (18) that is coupled to the voltage input (12) of the reset circuit (11).
申请公布号 US2011025365(A1) 申请公布日期 2011.02.03
申请号 US20090812581 申请日期 2009.01.09
申请人 AUSTRIAMICROSYSTEMS AG 发明人 WASER KARL GEORG
分类号 G01R31/26 主分类号 G01R31/26
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