PARALLEL TEST CIRCUIT

摘要

The circuit increases the operation speed by reducing the loading velocity and the number of AMP. The circuit includes the 1 st amplifier(31) which outputs output signal(out), the 2nd amplifier(32) which outputs /output signal, an inverter(33) which inverts parallel test signals(OPT), P1 which is applied to the parallel test refernce voltage(Vpt.ref) and connected to the positive input terminal of 1st amplifier(31), and P2 which is applied to the parallel test refernce voltage(Vpt.ref) and connected to the negative input terminal of 2nd amplifier(32).