| 摘要 |
Minimizing the power consumption in a field programmable gate array (FPGA) when used for convolution. The power consuming parts of the calculation are determined, and symmetry in those parts is exploited. For example, when multiplying by a filter have in common Values, the symmetry in the taps is detected. The values to be multiplied by the common tap values are edited and then the added value is multiplied. This minimizes the number of multipliers, thereby reducing power consumption.
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