发明名称 Methods of fabricating three-dimensional capacitor structures having planar metal-insulator-metal and vertical capacitors therein
摘要 Methods of forming a three-dimensional capacitor network may include forming a first horizontal MIM capacitor on a semiconductor substrate and forming a first interlayer insulating layer on the first horizontal MIM capacitor. A first vertical capacitor electrode is then formed in the first interlayer insulating layer and a second horizontal MIM capacitor is formed on the first interlayer insulating layer. This second horizontal MIM capacitor may be formed by forming an upper capacitor electrode and a lower capacitor electrode. The upper capacitor electrode may be electrically connected by the first vertical capacitor electrode to an upper capacitor electrode of the underlying first MIM capacitor. The lower capacitor electrode, which may be formed in the first interlayer insulating layer, may extend opposite the upper electrodes of the first and second MIM capacitors.
申请公布号 US7879681(B2) 申请公布日期 2011.02.01
申请号 US20080246093 申请日期 2008.10.06
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM YOON-HAE;KIM SUN-OO
分类号 H01L21/20 主分类号 H01L21/20
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