| 摘要 |
IN AN INTEGRATED CIRCUIT DEVICE THAT INCLUDES A FIRST MEMORY THAT IS CAPABLE OF INPUTTING DATA INTO AND /OR OUTPUTTING DATA FROM A SECOND MEMORY AND A PROCESSING UNIT IN WHICH AT LEAST PART OF AT LEAST ONE DATA FLOW IS CHANGEABLE, THE PROCESSING UNIT INCLUDES, IN ADDITION TO A DATA PROCESSING SECTION THAT PROCESSES DATA THAT IS INPUTTED FROM AND/OR OUTPUTTED TO THE FIRST MEMORY,A FIRST ADDRESS OUTPUTTING SECTION THAT OUTPUTS A FIRST ADDRESS OF DATA THAT IS INPUTTED AND/OR OUTPUTTED BETWEEN THE FIRST MEMORY AND THE DATA PROCESSING SECTION AND A SECOND ADDRESS OUTPUTTING SECTION THAT OUTPUTS A SECOND ADDRESS OF DATA THAT IS INPUTTED AND/OR OUTPUTTED BETWEEN THE FIRST MEMORY AND THE SECOND MEMORY.BY USING PART OF THE PROCESSING UNIT, WHERE A DATA FLOW CAN BE CHANGED OR RECONFIGURED, FOR CONFIGURING A CIRCUIT THAT CONTROLS THE MEMORIES,A CACHE MEMORY SYSTEM THAT IS OPTIMAL FOR THE PROCESSING EXECUTED BY THE INTEGRATED CIRCUIT DEVICE CAN BE CONFIGURED IN THE INTEGRATED CIRCUIT DEVICE.
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