Integrated circuit device with a memory that preserves its content independently of a synchronizing signal when given a self-control request

摘要

When a CPU (1) writes "10" into a register (RG) provided in a controller (5), an AND gate (10) receives a CPU clock mask signal (CMS1) having the logic of "0" by one of its input terminals and accordingly cuts off the supply of a clock signal CLK to the CPU (1). Then, the CPU (1) is suspended, thereby reducing power consumption of the CPU (1). To return out of this state, a user has only to input an interrupt request to the controller (5) through a terminal (T1). Receiving the request, the controller (5) outputs the CPU clock mask signal (CMS1) having the logic of "1" to one of the input terminals of the AND gate (10) so as to supply the CPU (1) with the clock signal (CLK) again. Upon restarting the supply of the clock signal (CLK), the CPU (1) starts an operation to implement the interrupt request. With this configuration, an integrated circuit device including a control circuit for controlling operations of a processing circuit and a memory circuit with excellent operability can be provided.