| 摘要 |
PROBLEM TO BE SOLVED: To provide a division management technology of a cache memory which is applicable even to a multi-process environment or a virtual machine use environment with small hardware costs.SOLUTION: A core ID-RAM 203 stores core ID for identifying the request source of a memory access request in association with each cache way of a cache block specified by a memory access request 708. A replacement core ID determination circuit 711 and a replacement way mask generation circuit 703 determines a replacement way candidate 709 upon the occurrence of a cache miss. An LRU selection circuit 704 selects and outputs replacement way instruction information 710 from a replacement way candidate 709. A cache control part 718 updates core ID stored in a core ID/RAM 203 with core ID 702 added to a memory access request 708 in the occurrence of a cache miss. |
