| 摘要 |
Semiconductor dice (100, 200) of integrated circuit chips are provided with solder bump pads (130, 230) distributed over active areas of the dice to supply the I/O interconnects without including peripheral wire bond pads. The dice are further provided with protective ESD structures (140p/140i, 240p/240i) arranged in a network that includes ESD structures that extend into the interior areas of the dice. This allows the ESD structures to be placed proximate to respective power and ground connections, and positioned to reduce an average interconnect length between interior bump pads and the ESD structures relative to an average path length between the interior bump pads and the die peripheral area.
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