发明名称 |
Phase-Locked Loop Modulation |
摘要 |
A phase-locked loop having: an oscillator for forming an oscillating output signal; a frequency divider connected to receive the output of the oscillator and frequency divide it by a value dependent on a division control signal; and a phase comparator for comparing the phase of the divided signal and a reference signal to generate a control signal, the operation of the oscillator being dependent on the control signal; the output data to form a divided signal a division ratio controller configured to, when clocked by an input signal, generate a series of output data for forming the division control signal; the phase-locked loop having: a first mode of operation in which the frequency divider is operable to frequency divide the output of the oscillator by a value dependent on the output of the division ratio controller; and a second mode of operation in which the frequency divider is not operable to frequency divide the output of the oscillator by a value dependent on the output of the division ratio controller, and the division ratio controller is clocked by a signal that is independent of the output of the oscillator. |
申请公布号 |
US2011019767(A1) |
申请公布日期 |
2011.01.27 |
申请号 |
US20090934617 |
申请日期 |
2009.03.13 |
申请人 |
CAMBRIDGE SILICON RADIO LIMITED |
发明人 |
LAMANNA PASQUALE;SORNIN NICOLAS |
分类号 |
H03D3/24;H03L7/08;H04L27/00 |
主分类号 |
H03D3/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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