发明名称 Controlling data accesses to hierarchical data stores to retain access order
摘要 Data storage circuitry for controlling access to data stored in a memory is disclosed. The data storage circuitry comprises: a data store for storing a subset of the data stored in the memory; access circuitry for receiving access requests and for outputting the requested data, at least some of the received access requests being ordered access requests requiring the accessed data to be output in a same order as the access requests are received in; control circuitry for controlling access to the data; and retrieval circuitry for retrieving the data from the memory; wherein the control circuitry is responsive to an access request received from the access circuitry to access the data store and in response to detecting a miss in the data store when the requested data is not stored in the data store to transmit the access request to the retrieval circuitry; the retrieval circuitry being configured to retrieve requested data from the memory in response to the access request and to store the data in the data store and being responsive to no asserted output inhibit signal associated with the data access request to transmit the retrieved data to the access circuitry for output and being responsive to an asserted output inhibit signal associated with the data access request not to transmit the retrieved data to the access circuitry; the data storage circuitry further comprising detection circuitry for detecting an earlier ordered access request that misses in the data store and a later ordered access request that hits while the earlier ordered access request is pending, the data storage circuitry being configured to halt the later ordered access request and in response to receipt of a subsequent ordered access request while the earlier ordered request is still pending to assert an output inhibit signal associated with the subsequent ordered access request and in response to detection of completion of the earlier ordered access request to deassert the output inhibit signal.
申请公布号 US2011022802(A1) 申请公布日期 2011.01.27
申请号 US20090458913 申请日期 2009.07.27
申请人 ARM LIMITED 发明人 ARSANTO FREDERIC JEAN DENIS;BOYER PIERRE MICHEL
分类号 G06F12/00;G06F12/08 主分类号 G06F12/00
代理机构 代理人
主权项
地址